The present invention relates generally to semiconductor memory devices having a memory circuit, such as a static random access memory (SRAM) or dynamic random access memory (DRAM), and more particularly to approaches for increasing access speeds for such devices.
Static random access memory (SRAM) circuits are highly valued in many applications due to their relatively fast access speeds. However, such fast access speeds typically come at the cost of increased current consumption and hence increased power consumption. With the advent of portable electronic devices, it has become an increasingly important goal to manufacture integrated circuits that consume less power. Thus, an increasingly important goal in SRAM circuit design has been to find ways to decrease the current and/or power consumption of such circuits, while maintaining relatively fast operating speeds.
SRAM circuits can typically include a number of SRAM memory cells. One particular type of SRAM memory cell is the six transistor (6-T) memory cell. One example of a 6-T memory cell is shown in FIG. 9a. The 6-T memory cell of FIG. 9a includes a pair of driver transistors Tr1 and Tr2 having cross-coupled gate-drain connections at nodes N1 and N2. Access transistors Tr3 and Tr4 can connect nodes N1 and N2 to digit lines D and /D. A 6-T memory cell may further include a pair of load devices. In some configurations, load devices can include transistors, while in other configurations load devices can include resistors. FIG. 9a illustrates an example of a 6-T memory cell with transistors Tr5 and Tr6 as load devices.
It is noted that while memory cells that include resistors as load devices are often referred to as xe2x80x9c4-Txe2x80x9d memory cells, to avoid confusion with xe2x80x9ctruexe2x80x9d 4-T memory cells discussed in more depth below, such four transistor, two resistor-type memory cells will also be considered 6-T cells for the purposes of this discussion.
The gates of access transistors Tr3 and Tr4 can be connected to a word line WL. Load devices (Tr5 and Tr6) can be connected between nodes N1 and N2 and a high power supply voltage. Driver transistors (Tr1 and Tr2) can have source-drain paths connected between nodes N1 and N2 and a low power supply voltage.
Another example of a 6-T memory cell is shown in FIG. 9b. The 6-T memory cell of FIG. 9b can include a pair of driver NMOS (n-channel insulated gate field effect transistor (IGFET)) type driver transistors (Tr1 and Tr2) having cross-coupled gate-drain connections at nodes N1 and N2. A pair of NMOS type access transistors (Tr3 and Tr4) can connect nodes N1 and N2 to digit lines D and /D. A 6-T memory cell may further include a pair of PMOS (p-channel IGFET) type load transistors Tr5 and Tr6 having cross-coupled gate-drain connections at nodes N1 and N2. The gates of NMOS type access transistors Tr3 and Tr4 can be connected to a word line WL. PMOS type load transistors Tr5 and Tr6 can be connected between nodes N1 and N2 and a high power supply voltage. NMOS type driver transistors (Tr1 and Tr2) can have source-drain paths connected between nodes N1 and N2 and a low power supply voltage.
SRAM circuits may select memory cells for access (e.g., a read or write operation) in a variety of ways. One type of access is provided by xe2x80x9ctruexe2x80x9d asynchronous SRAM circuits. A true asynchronous SRAM circuit can operate in response to applied input signals, and not in response to an external timing signal, such as a periodic clock signal. In many applications, true asynchronous SRAM circuits timing is based on a transition in an applied address value.
An example of a true asynchronous SRAM circuit operation is shown in FIG. 10. FIG. 10 is a timing diagram showing an address value ADD, a chip select signal /CS, a write enable signal /WE, a data input value DIN, and an indication of selected word line values (SEL WL). In FIG. 10, a chip select signal /CS and write enable signal /WE can be active (low in this case) and the address can make a transition. A data value (DATA) that is to be written can also be entered.
In response to the address transition, a word line WL and digit line pair (D and /D) can be selected. The input data (DATA) may then be written into the memory cell selected by the word line and digit line pair (D and /D).
A drawback to such an arrangement is that a memory cell can remain selected while the write enable signal /WE is active. During such a time period, a current can flow through a digit line from a de-selected memory connected to the same word line. Such a current can contribute to overall current consumption in a SRAM circuit.
Another drawback to a conventional true asynchronous SRAM circuit is the timing constraints that may be presented by such circuits. In particular, a true asynchronous SRAM circuit that is undergoing a write operation to one address may undergo a subsequent transition to a second address. To prevent the write data from being erroneously written into the second address, a SRAM circuit may include a specification TWR that indicates a minimum time between the termination of a write enable (/WE) pulse and a subsequent address transition. Such a TWR specification is shown in FIG. 10. A TWR requirement may increase the overall time required to access an SRAM cell, thus decreasing the operating speed of the SRAM device.
A second type of asynchronous SRAM circuit can operate internally in a similar fashion to a synchronous SRAM device. Namely, internal timing pulses can be generated to control read and/or write operations. However, unlike a synchronous SRAM circuit, such internal timing pulses are not generated in response to an externally applied periodic signal, but instead are generated in response to various transitions in other applied input signals. One such type of SRAM circuit can be referred to as a xe2x80x9cpulsexe2x80x9d word system. In a pulse word system, a memory cell can be selected at the particular time the read and write operations are taking place. More particularly, a pulse word system can generate timing pulses in response to transitions in address values and in response to transitions in write data values.
An example of a pulse word SRAM circuit operation is shown in FIG. 11a. FIG. 11a is a timing diagram showing an address value ADD, a chip select signal /CS, a write enable signal /WE, a data input value DIN, and an indication of selected word line values (PW). In FIG. 11a, a chip select signal /CS can be active (low in this case) while a write enable signal is inactive (high). In addition, the address can make a transition to a value A0. In response to the address transition, a pulse word signal (PULSE WL) can be activated, and data can be read from a memory cell corresponding to address A0.
Next, a write enable signal can be activated (transition low) while the chip select signal /CS is active (low) indicating a write operation. Further, an address can transition from an A0 value to a value A1. FIG. 11a particularly shows a xe2x80x9clongxe2x80x9d write operation where write data values may transition one or more times while a write enable signal is active. Consequently, a memory cell at address A1 can be written essentially multiple times.
In the above arrangement, because a memory cell is selected when the pulse word signal is active, the period of time during which a memory cell is selected can be less than that of a true asynchronous SRAM circuit. Consequently, current consumption can be reduced over a true asynchronous SRAM circuit approach.
Various examples of pulse word SRAM circuits are shown in Japanese Unexamined Patent Publication No. Hei 1-241089, Japanese Unexamined Patent Publication No. Hei 5-74162, and Japanese Unexamined Patent Publication No. Hei 8-222000.
However, as noted above, in a pulse word SRAM circuit a xe2x80x9clongxe2x80x9d write operation can take place. In a long write case, a pulse word signal (PW) can be generated for each transition in the write data. Consequently, the amount of time that a memory cell remains selected can be increased, essentially defeating the current saving features of a pulse word SRAM circuit. Still further, as the number of write data transitions increases, more current can be consumed.
It is further noted that a pulse word SRAM circuit may introduce time constraints between operations. More particularly, when a write operation occurs in a pulse SRAM, a precharge operation may be required before a subsequent read operation is performed. A precharge operation can precharge digit lines prior to a read operation. Thus, in a pulse word SRAM, reading may have to be postponed until after a precharge operation. For example, when the next read address is applied immediately after a write operation, the write data may still be on the digit line pair (D and /D) causing incorrect data to be read. Thus, it is necessary to precharge the digit line pair (D and /D) after a write operation. Therefore, a read following a write must be delayed by a TWR requirement to allow proper precharge levels to be reached on the digit line pair (D and /D). This can reduce the overall operating speed of a pulse SRAM circuit. While many conventional SRAM circuits include 6-T memory cells as previously described, in recent years a more compact memory cell has been proposed in an effort to provide higher density SRAM devices. The proposed memory cell is a xe2x80x9ctruexe2x80x9d four transistor (4-T) memory cell. A true 4-T memory cell can omit the load devices (e.g., transistors or resistors) present in a 6-T memory cell.
One example of a 4-T memory cell is shown in FIG. 12. The 4-T memory cell of FIG. 12 is shown to include a pair of driver transistors NMOS1 and NMOS2 having cross-coupled gates-drain connections at nodes N1 and N2. Driver transistors (NMOS1 and NMOS2) can be n-channel insulated gate field effect transistors (IGFETs). Access transistors PMOS1 and PMOS2 can connect nodes N1 and N2 to digit lines D and /D. Access transistors (PMOS1 and PMOS2) can be p-channel IGFETs.
The gates of access transistors (PMOS1 and PMOS2) can have gates that are connected to a word line. Driver transistors (NMOS1 and NMOS2) can have source-drain paths connected between nodes N1 and N2 and a low power supply voltage.
In a 4-T memory cell, data may be retained by supplying power to a digit line (D or /D) through a precharging circuit (not shown). With power supplied to a digit line, a subthreshold leakage current can pass across the source-drain path of an access transistor (PMOS1 of PMOS2) and thereby maintain a corresponding storage node (N1 or N2) at a high potential. In this way, data values can be maintained by a precharge operation.
While 4-T memory cells can provide for denser memory cell arrays, incorporating such memory cells into conventional SRAM circuit architectures can be problematic. For example, using a 4-T memory cell in a true asynchronous SRAM circuit described above, may lead to loss of data. In particular, when a word line is activated, a 4-T memory cell that is not connected to a selected column (e.g., its corresponding digit line pair is not selected) an have its nodes connected to digit lines, one of which can be at a relatively low potential. If a charged (high) node is connected to a digit line at a low power supply level by its corresponding access transistor, the charged node can be discharged, thereby destroying the data stored in the memory cell. For these reasons, it has been difficult to implement 4-T memory cells in a true asynchronous SRAM circuit.
In a true asynchronous SRAM circuit a write enable signal /WE controls the beginning and end of a write cycle. In a xe2x80x9clongxe2x80x9d write cycle one digit line from a digit line pair (D and /D) may be forced to a low power supply level for a long period of time. In an SRAM using 4-T memory cells, this can destroy high logic level data on an unselected memory cell in which the high logic level is stored at the node corresponding to the digit line forced to the low logic level.
FIG. 11b is a timing diagram illustrating an example of a xe2x80x9clongxe2x80x9d write cycle in a pulse word asynchronous SRAM circuit in which the above mentioned condition may occur. The timing diagram of FIG. 11b shows an address value ADD, a chip select signal /CS, a write enable signal /WE, a data input value DIN, and an indication of selected word line values (PW). The timing diagram of FIG. 11b also includes a digit line pair (D, /D) in which a true digit line D is shown as a solid line and a complementary digit line /D is shown as a dashed line. The timing diagram of FIG. 11b includes a xe2x80x9cDisturb Condition.xe2x80x9d During the disturb condition a data input value may change temporarily due to system noise. System noise can be caused by other chips that commonly use a data bus. If the input data DIN transitions are spaced in a short enough time period, a pulse word signal (PW) will be continuously high. Yet, the short data input value DIN glitches may not be long enough to switch the logic levels on the digit line pair (D, /D). This can be seen in FIG. 11b in which the time period of the xe2x80x9c0xe2x80x9d data value is much shorter than the xe2x80x9c1xe2x80x9d data value. If a 4-T memory cell is used, this can cause one of the digit lines (in this case /D) to be at a low logic level long enough to destroy data on unselected memory cells connected to the same digit line pair (D and /D). However, this will not cause a problem in a 6-T memory cell because a Vdd power supply line is routed separately to the memory cells and data can stay refreshed.
It is noted that while many of the above issues have been discussed for SRAM circuits, the same or similar issues may exist for other types of semiconductor memory devices. For example, when a write occurs in a Dynamic Random Access Memory (DRAM) the write data must achieve a sufficient voltage level in the selected memory cell before a precharge can occur. When a read is following a write, digit lines must be precharged before the read cycle can occur. Accordingly, a DRAM also has a timing specification TWR that indicates a minimum time from a write cycle to a subsequent read cycle. This TWR requirement may increase the overall time required to access a DRAM cell, thus decreasing the operating speed of the DRAM device.
In light of the above discussion it would be desirable to arrive at an SRAM and a DRAM circuit capable of achieving relatively fast access speeds.
Further, it would also be desirable to arrive at a SRAM circuit that can reduce current consumption over conventional approaches but maintain relatively fast access speeds.
Further, it would also be desirable to arrive at an asynchronous SRAM circuit that can include 4-T memory cells.
According to the disclosed embodiments, a semiconductor memory device may store write data provided in one write cycle, and then write the stored write data to a selected memory cell on a subsequent write cycle. Such a xe2x80x9cdelayedxe2x80x9d write operation may occur in response to a pulse signal generated internally to the semiconductor, memory device.
According to one aspect of the embodiments, a semiconductor memory device includes a static random access memory (SRAM) circuit having a memory cell array with a number of SRAM cells that are selected according to a received address. The SRAM may further include address registers that can store a write address value during one write cycle, and then provide the stored write address value on a subsequent write cycle.
According to another aspect of the embodiments, an SRAM circuit of the semiconductor memory device may include an address transition detector that can detect a change in the received address and generate a timing pulse in response thereto. The timing pulse can be used to generate timing signals to read data from and write data to the SRAM.
According to another aspect of the embodiments, the SRAM may include a write data register that can store write data during one write cycle for an address. If a read operation is subsequently performed to the same address, the stored write data can be provided as the read data.
According to another aspect of the embodiments, a SRAM circuit may store write data at the end of a write enable signal, preventing the unnecessary selection of memory cells during a long write operation in which write data values may change more than once during the write operation.
According to another aspect of the embodiments a SRAM circuit may generate internal timing signals that are not based on a synchronous external timing signal. Further, such timing signals can generate pulse word signals that can be used to read and write data. The SRAM circuit may further include a number of SRAM cells that are xe2x80x9ctruexe2x80x9d four transistor (4-T) memory cells. Such true 4-T memory cells can include two driver transistors having gate-drain connections that are cross-coupled to storage nodes, as well as two access transistors that connect the storage nodes to a digit line pair.
According to one aspect of the embodiments, the true 4-T memory cells can include driver transistors that are n-channel transistors and access transistors that are p-channel transistors.
According to another aspect of the embodiments, a semiconductor memory device may include a dynamic random access memory (DRAM) circuit having a memory cell array of DRAM memory cells, an address register circuit, and a data register circuit. An address register circuit may store a write address from a previous cycle. In response to a change in address, an address register circuit may output a stored write address. A data register circuit may store write data from a previous write cycle.
According to another aspect of the embodiments, a DRAM circuit of a semiconductor memory device may receive a write enable signal, and generate a row enable signal, a column enable signal, and a sense amplifier enable signal as pulse signals. In response to a row enable signal, column enable signal, and sense amplifier enable signal, write data previously stored in a data register circuit may be written to a location corresponding to a write address previously stored in an address register circuit.
According to another aspect of the embodiments, a DRAM circuit of a semiconductor memory device may perform a refresh operation following a data write operation. A data write operation may be a delayed write operation as described above.